1. Field of the Invention
The present invention relates to a semiconductor memory device, e.g., a NOR type nonvolatile semiconductor memory device.
2. Description of the Related Art
In a semiconductor memory device in which bit lines having even numbers (even-numbered bit lines) and bit lines having odd numbers (odd-numbered bit lines) are separately allocated to input/output lines I/O, data write to memory cells is performed as follows. A write load circuit supplies a write voltage to a data line by selecting an upside or downside memory cell array by a switching transistor. This write voltage supplied to the data line charges a bit line selected by a column selection transistor. The charged bit line writes data in memory cells.
When writing a checker pattern in a memory cell array of the semiconductor memory device described above, the data is written by using an even-numbered bit line, e.g., a data line DL0, with respect to the nth one of word lines WL. That is, when the product has 16-bit input/output lines I/O, only 8 bits of low-order input/output lines I/O of the write load circuit are active, and 8 bits of high-order input/output lines I/O of the write load circuit are disabled.
As described above, the conventional semiconductor memory device writes the checker pattern by using only 8 bits of the low-order input/output lines I/O. This makes it impossible to reduce the write time required to write the checker pattern. Note that the checker pattern is a pattern in which data are alternately inverted between adjacent memory cells, and is test data that is written in a memory cell array at the time of testing and used to verify whether expected values are written.
Also, one prior art related to the present invention has proposed a semiconductor memory that comprises a first switching means for selecting odd-numbered or even-numbered word lines in accordance with a pattern signal in a test mode, and a second switching means for applying complementary data signals to the odd-numbered and even-numbered bit lines in accordance with the pattern signal, and writes the checker pattern in all memory cells by performing a write operation twice (Jpn. Pat. Appln. KOKAI Publication No. 2001-236795).